View CXD1961Q_5790290.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? pe96417-te preliminary sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. dvb-s front-end ic (qpsk demodulator + fec) CXD1961Q absolute maximum ratings (ta=25?, gnd=0v) supply voltage v dd ?.5 to 4.6 v input voltage v in ?.5 to v dd +0.5 v output voltage v out ?.5 to v dd +0.5 v i/o voltage v i/o ?.5 to v dd +0.5 v cpu i/f pin v cpuif ?.5 to 5.5 v operating temperature topr 0 to +75 ? storage temperature tstg ?5 to +150 ? dc recommended operating conditions (ta=0? to 75?, gnd=0 v) supply voltage v dd 3.15 to 3.45 v input hi-level v ih v dd ?.7 to v dd +0.5 v input lo-level v il 0.3 to v dd +0.2 v description the CXD1961Q is a single chip dvb satellite broadcasting front-end ic, including dual adc for analog i/o inputs, qpsk demodulator, viterbi decoder, de-interleaver, reed-solomon decoder and energy dispersal descrambler. it is suitable for use in a dvb integrated receiver decoder. features dual 6 bit a/d converters qpsk demodulator multi-symbol rate operation nyquist roll off filter ( a = 0.35) clock recovery circuit carrier recovery circuit agc control circuit viterbi decoder constraint length k =7 punctured rate r = 1/2 ?/8 truncation length 144 punctured rate search function ber monitor de-interleaver packet synchronization convolutional de-interleaver reed-solomon decoder (204, 188) energy dispersal descrambler cpu interface l 2 c bus interface/8 bit cpu bus ttl interface level (5v input capability) jtag(ieee std 1149.1?990) test mode package : qfp-100pin single +3.3v power supply symbol rate max:32msps min:tbd power consumption tbd 0.4um cmos technology applications dvb-s set top box (satellite) 100 pin qfp (plastic)
? CXD1961Q block diagram typical application block diagram 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 12 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 20 21 22 23 24 25 26 27 28 29 30 19 51 52 53 54 55 56 57 59 58 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 pll vco nco qpsk demodulator sampling clock 2ch adc analog i/q digital filter viterbi decoder de-interleaver jtag reed-solomon decoder cpu i/f energy dispersal decoded data & clock 8bit cpu bus oscillator l 2 c bus saw lnb vco pll lpf lpf lpf osc amp reference micro controller i/q detector qpsk+fec sony CXD1961Q data clock crystal 90
? CXD1961Q pin configuration 92 91 90 89 88 87 86 85 84 83 82 81 100 99 98 97 96 95 94 93 22 21 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 23 24 25 26 27 28 29 30 73 75 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 74 76 77 78 79 80 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 v dd 10 cr7 cr6 cr5 cr4 v ss 9 v dd 9 cr3 cr2 cr1 cr0 ckv agcpwm v ss 8 v dd 8 test5 test4 xi xo v ss 7 v dd 7 sda scl a dd 3 a dd 2 a dd 1 v ss 6 v dd 6 a dd 0 cs ds rw d7 d6 d5 v ss 5 v dd 5 d4 d3 d2 d1 d0 data7 data6 data5 v ss 4 v dd 4 data4 data3 data2 data1 data0 pkterr bytclk pktclk v ss 3 v dd 3 te reset ck8out tdi tdo tms tck v ss 2 v dd 2 sen sclk sdata v ss 1 v dd 1 test3 test2 test1 pllsel cpusel v ss 0 v dd 0 rb0 avs0 vcoen opout iin avd0 rt0 rb1 avs1 qin avd1 rt1 avs2 opx in vcoc avd2 cpout v ss 11 v dd 11 test7 test6 v ss 10
? CXD1961Q pin description no. symbol i/o description 1 avs0 analog ground 2 rb0 adc0 bottom reference voltage 3v dd 0 digital power supply (+3.3 v) 4v ss 0 digital ground 5 cpusel i cpu interface select (l : i 2 c bus) 6 pllsel i connect digital ground 7? test1? i test input (connect digital ground) 10 v dd 1 digital power supply (+3.3 v) 11 v ss 1 digital ground 12 sdata o sony internal use 13 sclk o sony internal use 14 sen o sony internal use 15 v dd 2 digital power supply (+3.3 v) 16 v ss 2 digital ground 17 tck i jtag test clock 18 tms i jtag test mode select 19 tdo o jtag test data output 20 tdi i jtag test data input 21 ck8out o divide by 8 clock of crystal clock 22 reset i reset input (l : reset) 23 te i test enable (h : test enable) 24 v dd 3 digital power supply (+3.3 v) 25 v ss 3 digital ground 26 pktclk o r/s packet clock 27 bytclk o r/s byte clock 28 pkterr o r/s uncorrectable packet flag 29?3 data0? o r/s data output (data0 : lsb) 34 v dd 4 digital power supply (+3.3 v) 35 v ss 4 digital ground 36?8 data5? o r/s data output (data7 : msb) 39?3 d0?4 i/o 8 bit cpu bus data i/o (d0 : lsb) 44 v dd 5 digital power supply (+3.3 v) 45 v ss 5 digital ground 46?8 d5?7 i/o 8 bit cpu bus data i/o (d7 : msb) 49 rw i 8 bit cpu bus read/write (h : read) 50 ds i 8 bit cpu bus data strobe 51 cs i 8 bit cpu bus chip select 52 a dd 0 i 8 bit cpu bus address0 (lsb) 53 v dd 6 digital power supply (+3.3 v) 54 v ss 6 digital ground
? CXD1961Q no. symbol i/o description 55?7 add1? i 8 bit cpu bus address1? (add3 : msb) 58 scl i i 2 c bus serial clock 59 sda i/o i 2 c bus serial data 60 v dd 7 digital power supply (+3.3 v) 61 v ss 7 digital ground 62 xo o oscillator output (for crystal) 63 xi i oscillator input (for crystal) 64, 65 test4, 5 o test output (v ss level) 66 v dd 8 digital power supply (+3.3 v) 67 v ss 8 digital ground 68 agcpwm o pwm output for agc 69 ckv o sampling clock monitor output 70?3 cr0? o clock recovery data 0? (cr0 : lsb) 74 v dd 9 digital power supply (+3.3 v) 75 v ss 9 digital ground 76?9 cr4? o clock recovery data 4? (cr7 : msb) 80 v dd 10 digital power supply (+3.3 v) 81 v ss 10 digital ground 82, 83 test6, 7 o test output (v ss level) 84 v dd 11 digital power supply (+3.3 v) 85 v ss 11 digital ground 86 cpout o pll charge pump output 87 avd2 analog power supply (+3.3 v) 88 vcoc i vco control voltage input 89 opxin i embedded op-amp negative input 90 opout o embedded op-amp output 91 avs2 analog ground 92 vcoen i vco enable (h : enable) 93 rt1 adc1 top reference voltage 94 avd1 analog power supply (+3.3 v) 95 qin i analog q input (adc1 input) 96 avs1 analog ground 97 rb1 adc1 bottom reference voltage 98 rt0 adc0 top reference voltage 99 avd0 analog power supply (+3.3 v) 100 iin i analog input (adc0 input) note) apply 0.1 ? capacitor to every power supply terminal. apply 0.1? capacitor to rb0, rt0, rb1, rt1 for stable a to d conversion.
? CXD1961Q cpu interface register sub r/w msb 7 654321 lsb 0 address 0 r adc_in7 adc_in6 adc_in5 adc_in4 adc_in3 adc_in2 adc_in1 adc_in0 1 r becnt15 becnt14 becnt13 becnt12 becnt11 becnt10 becnt9 becnt8 2 r becnt7 becnt6 becnt5 becnt4 becnt3 becnt2 becnt1 becnt0 3 r qsync afc3 afc2 afc1 afc0 vsync rsync bem_end 4 w agc7 agc6 agc5 agc4 agc3 agc2 agc1 agc0 5 w vs_n4 vs_n3 vs_n2 vs_n1 vs_n0 rate2 rate1 rate0 6 w qs_n3 qs_n2 qs_n1 qs_n0 ac2 ac1 bc2 bc1 7 w ak2 ak1 s_inv agc_inv agc_mod timer2 timer1 timer0 8 w pll_ctl mon_sw vs_t3 vs_t2 vs_t1 vs_t0 ce_lev1 ce_lev0 9 w df_skip dout_inv rs_skip ssel afc_mod ber_t2 ber_t1 ber_t0 a w sfd18 sfd17 sfd16 sfd15 sfd14 sfd13 sfd12 sfd11 b w sfd10 sfd9 sfd8 sfd7 sfd6 sfd5 sfd4 sfd3 c w sfd2 sfd1 sfd0 pcd2 pcd1 pcd0 ref_sel ref_lsb d w nc023 nc022 nc021 nc020 nc019 nc018 nc017 nc016 e w nc015 nc014 nc013 nc012 nc011 nc010 nc09 nc08 f w nc07 nc06 nc05 nc04 nc03 nc02 nc01 nc00 note) 1. above registers are shared by i 2 c bus interface and 8 bit cpu bus interface. 2. to select cpu interface, use cpusel (pin 5) ; h : 8 bit cpu bus / l : i 2 c bus. 3. i 2 c bus interface slave address; msb 6 5 4 3 2 1 lsb 0 r/w 1101110 write mode : dc (hex) read mode : dd (hex)
? CXD1961Q fig. 1 v sync threshold (error counter preset data) (ex. vs_n (4 : 0)=(1, 1, 0, 0, 1) limit=0 2 9 +0 2 8 +1 2 7 +1 2 6 +0 2 5 =192) cpu interface register brief explanation a dd 0 a dd 1, 2 a dd 3 a dd 4 a dd 5 a dd 6 a dd 7 a dd 8 a dd 9 a dd a a dd a, b, c a dd c a dd d, e, f adc_in (7 : 0) becnt (15 : 0) qsync afc (3 : 0) vsync rsync bem_end agc (7 : 0) vs_n (4 : 0) rate (2 : 0) qs_n (3 : 0) ac (2 : 1), bc (2 : 1) ak (2 : 1) s_inv agc_inv agc_mod timer (2 : 0) pll_ctl mon_sw vs_t (3 : 0) ce_lev (1 : 0) df_skip dout_inv rs_skip ssel afc_mod ber_t (2 : 0) hs_pll sfd (17 : 11) pcd (2 : 0) ref_sel ref_lsb nc0 (23 : 0) adc input level (i 2 +q 2 at qpsk demodulator) bit error count at qpsk demodulator output qpsk synchronization flag (h : in sync.) auto frequency control data viterbi dec. synchronization flag (h : in sync) reed-solomon dec. synchronization flag (h : in sync) bit error monitor enable flag (h : enable) (when agc mode is h) agc gain control data (when agc mode is l) reference data for self agc v sync threshold bit error count (see fig. 1) punctured rate (see fig. 2) threshold data for qpsk sync. judgement (see fig. 3) parameter for carrier recovery loop filter (see fig. 4) parameter for clock recovery loop filter (see fig. 4) i/q exchange (h : enable) agc control voltage polarity (h : positive) h : controlled by cpu (slave) l : self agc mode (master) timer for agc master mode (see fig. 5) for sony internal use (input 0 for norma use) for sony internal use (input 0 for norma use) monitor period for viterbi sync. (see fig. 6) clock recovery error feed back level (see fig. 7) digital filter skip mode (h : enable) data output timing invert (h : falling edge) r/s decode skip mode (h : enable) for sony internal use (input 0 for normal use) for sony internal use (input 0 for normal use) monitor period for bit error count (see fig. 8) for sony internal use (input 0 for normal use) for sony internal use (input 0 for normal use) for sony internal use (input 0 for normal use) for sony internal use (input 0 for normal use) for sony internal use (input 0 for normal use) sampling frequency 2*fs=nc0 (0 : 23)*8*fxtal/2 24 (fxtal=crystal frequency) register vs_n4 vs_n3 vs_n2 vs_n1 vs_n0 limit 2 9 2 8 2 7 2 6 2 5 max. : 992 min. : 32 punc. rate 1/2 2/3 3/4 4/5 5/6 6/7 7/8 auto rate2 0 0 0 1 1 1 1 0 rate1 0 1 1 0 0 0 1 0 rate0 1 0 1 0 1 0 1 0 fig. 2 punctured rate
? CXD1961Q fig. 3 qpsk synchronization monitor qsync threshold (qs_n3) 2 7 +(qs_n2) 2 6 +(qs_n1) 2 5 +(qs_n0) 2 4 qsync monitor period 256 (fix) fig. 4 costas loop filter co-efficiency parameter (0, 0) (0, 1) (1, 0) (1, 1) item (ac2, ac1) 1 1/2 1/4 1/8 carrier recovery iir filter (bc2, bc1) 1 2 4 8 carrier recovery tracking range (ak2, ak1) 1 1/2 1/4 1/8 clock recovery iir filter fig. 5 timer period (sampling frequency = 60 mhz) timer2 1 1 1 1 0 0 0 0 timer1 1 1 0 0 1 1 0 0 timer0 1 0 1 0 1 0 1 0 period (ms) 140 70 35 17.5 8.75 4.38 2.19 1.09 frequency (khz) 7.14 14.3 28.6 57.1 114 229 457 914 fig. 6 v sync monitor period (measurement period counter preset data) (ex. vs_t (3:0)=(0, 1, 1, 1) ? limit=1 2 12 +0 2 11 +0 2 10 +0 2 9 =4096) register vs_t3 vs_t2 vs_t1 vs_t0 period (viterbi clock) 2 12 2 11 2 10 2 9 fig. 7 clock recovery error data (8 bit) feed back level 543210 nco 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 ce_lev (1, 1) (1, 0) (0, 1) (0, 0) fig. 8 bit error monitor period (viterbi clock) ber_t2 1 1 1 1 0 0 0 0 ber_t1 1 1 0 0 1 1 0 0 ber_t0 1 0 1 0 1 0 1 0 period 2 19 2 18 2 17 2 16 2 15 2 14 2 13 2 6 max. : 6656 min. : 512 (viterbi clock)
? CXD1961Q functional description (1) cpu interface CXD1961Q has two cpu interface, an 8 bit cpu bus and an i 2 c bus interface. fix cpusel (pin 5) to dc l or h level depending on the choice of bus. cpusel=l : i 2 c bus / h : 8 bit bus i 2 c bus interface the CXD1961Q's slave address is "1101110", and the read/write operation is based on philips standard. in write operation, the second byte is input as the sub-address of the start position. the 3rd byte then forms the data to be written to the start register. successive data bytes are written to successive sub-address register. sta : start condition ack : acknowledgment by CXD1961Q stp : stop condition note) registers of sub-address 0hex to 3hex are read only before read operation, the sub-address of the start register to be read is input by using write operation, and terminated by a stop condition. read operation then begins with the second byte which is the data of the start register. data of successive sub-address registers are read successively following by the second byte. note) registers of sub-address 4hex to fhex are write only s slave a sub- a input data a input data aas t address 0 c address c for "n" c for "n+1" c ? c t a 1101110 k nhex k k k k p s slave a sub- a s t address 0 c address c t a 1101110 k nhex k p s slave a output data a output data aas t address 1 c from "n" c from "n+1" c ? c t a 1101110 k k k k p
?0 CXD1961Q 8 bit cpu bus interface t1 t2 t3 t4 t5 t6 valid input valid address (write cycle) ds rw d [7:0] a dd [3:0 ] cs t1 t2 t3 t4 t5 t6 valid output valid address (read cycle) ds rw d [7:0] a dd [3:0] cs timing description min (nsec) max (nsec) t2?1 address, cs to data valid 25 t3?1 r/w to ds 24 t3?2 data valid to ds 10 t4?3 ds pulse width 70 t5?4 data hold time 21 t6?4 address, cs, r/w hold time 24 timing description min (nsec) max (nsec) t2?1 address, cs, r/w to ds 24 t3?2 ds to data valid 75 t4?2 ds pulse width 105 t5?4 data hold time 24 t6?4 address, cs, r/w hold time 24 note) registers of address 0hex to 3 hex are read only note) registers of address 4hex to fhex are write only
?1 CXD1961Q (2) analog to digital converters the dual 6 bit a to d converters quantize the analog i/q input data. the input range of the adc's is determined by external resistors. rt0 (rt1) is the top reference voltage, and rb0 (rb1) is the bottom reference voltage. rt0 (rt1) and rb0 (rb1) are connected internally with a 320 (typical value) resistor. in the example shown in the following figure, input range is approximately 1.1 v, and center voltage 1.65 v. (3) agc input signal level of the a to d converter is estimated by calculating i 2 +q 2 in 16 bit precision, and the upper 8 bits of the estimated data are sent via the cpu i/f as adc_in [7:0]. CXD1961Q has two agc modes that can be selected by agc_mod. in agc slave mode, adc_in[7:0] is checked and an appropriate gain level agc[7:0] is returned by the micro controller. this value is converted into 8 bit pwm format and output from agcpwm (pin 68). in agc master mode, reference level agc[7:0] is set via the cpu i/f and compared to adc_in[7:0] internally. the updated gain level is then output at the agcpwm pin. in normal operation, adc_in[7:0] becomes almost equal to reference level. in agc master mode, agc control interval is set by timer[2:0]. in both modes, agcpwm output should be low pass filtered, and if needed, the level should be converted to satisfy the agc gain control range. depending on agc_inv, the polarity can be inverted. (h:positive / l:negative) cpu register adc_in [7 : 0] ? a dd 0h agc [7 : 0] ? a dd 4h agc_inv ? a dd 7h agc_mod ? a dd 7h timer [2 : 0] ? a dd 7h note) adc input range is subject to temperature and v dd level. avs (0v) avd (+3.3v) rb rt CXD1961Q top reference level input range bottom reference level 320 w 330 w 330 w reference level input signal level adc_in [7 : 0] to adc input range ratio 0f 0.25 3f 0.5 7f 0.7 ff 1.0 or over range
?2 CXD1961Q (4)clock recovery initial sampling clock frequency is set by a 24 bit word via the cpu i/f. this 24 bit word is written to the nco(numerically controlled oscillator). the sampling frequency is: fsample= 8*nco [23:0]*fxtal/2 24 where: nco [23:0] is the parameter for sampling frequency, "8" is the divider gain of the pll, fxtal is the reference crystal frequency, whose value should be more than 30mhz (32mhz is recommended). the internal digital clock recovery loop feeds clock error data to the above nco to provide sampling timing correction . ak [2:1] is the loop filter coefficient and ce_lev [1:0] is the loop gain. this value limits clock recovery range and resolution. (see the cpu interface register brief explanation fig.7) sampling clock is output from ckv (pin 69). cpu i/f register ak [2:1] ? a dd 7h ce_lev [1:0] ? a dd 8h nco [23:0] ? a dd d, e, fh (example) ce_lev [1:0]=(0,1), nco [23:0]=(001110000000000000000000), fxtal=32 mhz sampling frequency = 8*(2 21 +2 20 +2 19 )*32*10 6 /2 24 = 2 3 *7*10 6 = 56*10 6 ? 56 mhz clock recovery range = 2 9 /(2 21 +2 20 +2 19 ) = 1/2 10 /7 = 139.5..*10 ? ? ?40 ppm clock recovery = 8*2 1 *32*10 6 /2 24 = 30.5. . . ? 31 hz resolution (5)carrier recovery the analog i/q inputs have a carrier offset frequency, which is not corrected by the tuner's pll synthesizer. the offset is compensated by a costas loop, using a frequency multiplier, loop filter and the nco. ac [2:1] is the coefficient of the loop filter and bc [2:1] is the loop gain parameter. qpsk synchronization(qsync) is determined by monitoring the output of loop filter. the internal sync detector monitors 256 cycles, and checks the value with the threshold set by qs_n [3:0]. in qpsk synchronization, afc [3:0] indicates the offset proportional value which remains at that point. this value is the average data of the loop filter output. if afc3(=msb) is high, tuner pll has a negative offset to the carrier frequency , and vice versa if afc3 is low. by feeding the afc [3:0] to the tuner's pll synthesizer, carrier offset can be corrected with the pll step size. cpu i/f register qsync,afc [3:0] ? a dd 3h qs_n [3:0], ac [2:1], bc [2:1] ? a dd 6h
?3 CXD1961Q (6)viterbi decoder by using qpsk demodulated data and viterbi decoded data, the existence of errors is detected. bit error measured over a certain period is used to determine the correct punctured rate and phase synchronization as well as bit error rate (ber). vs_n[4:0] is used to set the error count threshold, and vs_t[3:0] is used to set the error count duration. (see fig.1 and fig. 6 of cpu interface register brief explanation) for example) vs_n[4:0]=(1, 1, 0, 0, 1) ? error count threshold =192 vs_t[3:0] =(1, 0, 1, 1) ? error count duration = 2048 in this case, bit error is checked for 2048 cycles. if the error count is less than 192, CXD1961Q judges that punctured decoding is in sync and vsync goes high. punctured rate is set by rate[2:0]. when a certain rate is set by rate[2:0], only punctured phase search is performed. punctured rate and phase search is performed if rate[2:0] is set to (0, 0, 0). CXD1961Q has 2 16 (= 65536) bit counter for ber estimation. ber monitor period is set by ber_t[2:0] (see fig. 8), and the error count is read by cpu i/f as becnt[15:0]. if bem_end is low, punctured rate or phase search is not finished and the error count is not reliable at that moment. cpu i/f register bercnt[15:0] ? a dd 1, 2h vsync ? a dd 3h bem_end ? a dd 3h vs_n[4:0] ? a dd 5h vs_t[3:0] ? a dd 8h ber_t[2:0] ? a dd 9h (7) packet synchronization and de-inter leaver 2 dimensional sync protection starts once sync word 47 hex or inverted sync word b 8 hex is detected. in this algorithm, sync status changes with hysteresis depending on sync or non-sync detection every 204 byte, so that the probability of false-lock or sync-loss is minimized. when the packet synchronization is achieved,the convolutional de-inter leaver (forney, depth=12) starts operating. (8) reed - solomon decoder the galois field is generated by f(x) = x 8 +x 4 +x 3 +x 2 + 1 code is generated by g(x) = (x- a 0 )(x- a 1 )(x- a 2 ) ??(x- a 15 ) if rs_skip is high, no correction is performed. cpu i/f register rs_skip ? a dd 9h (9) energy dispersal energy dispersal descrambling is represented by the polynomial x 15 + x 14 +1. initial sequence is loaded when inverted sync word b8hex is detected. 1 dimensional sync protection circuit checks the inverted sync word every 8 packets. when it is in sync, rsync goes high. even if the sync is lost, the initial sequence continues to be loaded at previous time step. cpu i/f register rsync ? a dd 3h
?4 CXD1961Q (10) output data format the following figure shows the output format of bytclk, pktclk, pkterr. bytclk is generated by dividing the internal viterbi clock by 8. data output data[7:0] is output in sync with bytclk. dout_inv determines whether data[7:0] is output on the rising edge or the falling edge of bytclk. pktclk high- time is equal to 188 data bytes period and pktclk low-time is equal to 16 parity bytes period. pkterr goes h if an uncorrectable error packet is encountered. cpu i/f register dout_inv ? a dd 9h bytclk and pktclk have varying forms, depending on the punctured rate. the following figure shows minimum and maximum values for each rate. one unit represents 1 sampling clock (=2 * symbol rate) cycles. bytclk pktclk pkterr no error data parity data data pa parity uncorrectable error correctable error bytclk pktclk period high-time low-time period high-time low-time min. max. min. max. min. max. min. max. min. max. min. max. r=1/2 16 16 8 8 8 8 3264 3264 3008 3008 256 256 r=2/3 12 12 6 6 6 6 2448 2448 2256 2256 192 192 r=3/4 10 11 5 6 5 6 2176 1276 2005 2006 170 171 r=4/5 10 10 5 5 5 5 2040 2040 1880 1880 160 160 r=5/6 9 10 4 5 4 5 1948 1949 1804 1805 153 154 r=6/7 9 10 4 5 4 5 1904 1904 1754 1755 149 150 r=7/8 9 10 4 5 4 5 1865 1866 1718 1719 146 147 saclk (for example) viterbi clock byteclock byte clock r=1/2 r=7/8 viterbi clock
?5 CXD1961Q sony code eiaj code jedec code package material lead treatment lead material package weight epoxy/phenol resin solder plating 42 alloy package structure detail a lqfp-100p-l01 * qfp100-p-1414-a 100pin lqfp (plastic) 16.0 0.2 * 14.0 0.1 75 51 50 26 25 1 76 0.5 0.08 0.18 ?0.03 + 0.08 (0.22) a 1.5 ?0.1 + 0.2 0.127 ?0.02 + 0.05 0.5 0.2 (15.0) 0?to 10 0.1 0.1 0.5 0.2 100 0.1 note: dimension * ?does not include mold protrusion. package outline unit : mm

▲Up To Search▲

Price & Availability of CXD1961Q

	To Download CXD1961Q Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .